Conventional semiconductor devices such as integrated circuits (IC) generally include a semiconductor substrate, usually a silicon substrate, and several sequentially formed conductive material layers separated by insulating material layers. Conductive material layers, or interconnects, form the wiring structure of the IC. A wiring structure is isolated from the neighboring wiring structures by insulating layers or interlayer dielectrics. A dielectric material that is commonly used in silicon ICs is silicon dioxide, although there is a current trend to replace at least some of the standard dense silicon dioxide material in the IC structure with low-k dielectric materials. This replacement is necessary in high performance ICs where the RC time constant needs to be reduced to increase the speed of the circuit. To reduce the capacitance, the high dielectric constant materials in the interconnect structure needs to be replaced with low-k materials.
There are various low-k materials that have been used in the industry. These are organic, inorganic, spin-on and CVD materials. Some low-k materials are porous with dielectric constants well below 3.0. As is well known, implementing low-k dielectrics presents many manufacturing challenges. For example, their low mechanical strength and/or poor adhesion to the substrate present some challenges in the semiconductor industry.
IC interconnects are formed by filling a conductor such as copper in features or cavities etched into the dielectric interlayers by a metallization process. Copper is becoming the preferred conductor for interconnect applications because of its low electrical resistance and desired electromigration property. Currently, electroplating is the preferred process for copper metallization.
In the typical IC, multiple levels of interconnect structures extend laterally with respect to the substrate surface. Interconnects formed in sequential layers can be electrically connected using features such as vias or contacts. In a typical interconnect fabrication process, an insulating layer is first formed on the semiconductor substrate. Patterning and etching processes are then performed to form features or cavities such as trenches, vias, and pads etc., in the insulating layer. Then, copper is electroplated to fill the features. In such electroplating process, the workpiece or wafer (these terms are used interchangeably herein) is placed on a wafer carrier and a cathodic (−) voltage with respect to an electrode is applied to the wafer surface while the electrolyte or the electrolyte solution wets both the wafer surface and the electrode.
Once the plating process is over, a material removal step such as a chemical mechanical polishing (CMP) process is performed to remove the excess copper layer (also called copper overburden) from the top surfaces (also called field region) of the wafer, thereby leaving copper only within the features. An additional material removal step is then performed to remove other conductive layers such as the barrier/glue layers that are on the field regions. In this manner, deposited copper within the features are physically as well as electrically isolated from each other. It should be noted that material removal processes include, but are not limited to, CMP, electroetching and etching processes. Furthermore, processes for removing both copper and barrier/glue layers from the field regions in one step may also be employed.
During CMP, the plated wafer surface is pressed on a moving polishing pad or a polishing belt and planarized while the wafer is rotated. As mentioned above, this process electrically isolates the copper deposited into various features on a given interconnect level. After repeating these processes several times, multi-level interconnect structures may be formed in which copper within via or contact features may electrically connect the various interconnect levels. However, the CMP processes can create problems with low-k dielectrics because of the mechanical force applied on the wafer surface during the processes. For instance, during CMP, the low-k materials may be stressed and delaminate or other defects may result due to the low mechanical strength or poor adhesion of the low-k materials. The longer the CMP process, these problems become more prominent. Accordingly, it is desirable to reduce the CMP time and force applied on the wafers, especially those using low-k insulators.
There are efforts to lower the force or pressure used in CMP processes. There is also efforts to employ etching or electroetching techniques instead of CMP to remove the copper overburden from the field regions of plated substrates.
The adverse effects of CMP may be minimized or overcome by employing a planar copper deposition approach that can provide thin layers of planar copper on the workpiece surface. One such planar deposition technique is the Electrochemical Mechanical Deposition (ECMD) method. In one aspect of ECMD, a workpiece-surface-influencing device (WSID) such as a mask, pad or a sweeper is used during at least a portion of the electrodeposition process when there is physical contact and relative motion between the workpiece surface and the WSID. Descriptions of various planar deposition methods and apparatus can be found in the following patents and pending applications, all commonly owned by the assignee of the present invention: U.S. Pat. No. 6,176,992 entitled “Method and Apparatus for Electrochemical Mechanical Deposition”; U.S. application Ser. No. 09/740,701 entitled “Plating Method and Apparatus that Creates a Differential Between Additive Disposed on a Top Surface and a Cavity Surface of a Workpiece Using an External Influence,” filed on Dec. 18, 2001, now U.S. Pat. No. 6,534,116; and U.S. application Ser. No. 09/961,193 entitled “Plating Method and Apparatus for Controlling Deposition on Predetermined Portions of a Workpiece,” filed on Sep. 20, 2001, now U.S. Pat. No. 6,921,551. The methods disclosed in these patent/applications can be used to deposit metals in and over cavity sections on a workpiece in a planar manner.
Using ECMD methods, the workpiece surface is wetted by the electrolyte and is rendered cathodic with respect to an electrode, which is also wetted by the electrolyte. This results in material deposition on the surface of the workpiece. These techniques can also be used for electroetching by reversing the polarity of the applied voltage and rendering the workpiece surface more anodic compared to the electrode. Very thin planar deposits can be obtained by first depositing a planar layer using an ECMD technique and then electroetching this planar film in the same electrolyte or in a special electro-etching or electro-polishing solution by reversing the applied voltage. In this manner, the thickness of the deposited layer may be reduced in a planar manner. In fact, this etching process can occur until all/most of the metal on the field regions are removed. It should be noted that a WSID may or may not be used during the electroetching process since planar etching can be achieved with or without the WSID.
In greater detail, during ECMD, the workpiece surface is pushed against the surface of the WSID or vice versa for at least portion of the time when the surface of the workpiece is swept by the WSID. Planar deposition occurs due to the sweeping action as described above. It is also desirable to reduce the force applied on the workpiece surface by the sweeper surface, especially for workpieces with structurally weak low-k materials. When the force is reduced, however, the integrity of the contact between the workpiece surface and the sweeper surface need to be preserved. In other words, this physical contact needs to be uniform and repeatable for optimal results. Accordingly, there is need for an improved ECMD method and apparatus for minimizing the force applied to the substrate surfaces during planar metal deposition or electroetching while keeping this force uniformly distributed over the sweeper area.